1. Field of the Invention
The present invention is related to a layered semiconductor wafer and a process for its production.
2. Background Art
SOI wafers (“semiconductor on insulator”) comprise a substrate wafer (“handle wafer” or “base wafer”), generally consisting of monocrystalline silicon, a layer of an electrically insulating material (the so-called “buried oxide layer”, BOX) and a superficial layer of semiconductor material (“top layer” or “device layer”) connected thereto, which represents the so called active layer that is provided for the production of electronic components.
SOI wafers can be manufactured by various methods. One widely used method is to transfer a thin layer of semiconductor material from a donor wafer to the substrate wafer. Prior to this transfer, the surfaces of the donor wafer or of the substrate wafer or both are oxidized in order to form the insulating layer. This method is referred to as “layer transfer”. In a second method, an insulating layer can be directly formed within a silicon substrate wafer by implanting oxygen ions into one of its surfaces and annealing the substrate wafer subsequently in order to form a silicon oxide layer. This method is called “SIMOX”.
The first method (layer transfer) is costly due to work intensive process steps. It is well developed for silicon and within limits for germanium but not for alternative semiconductors like gallium nitride (GaN), zinc oxide (ZnO) or other materials to be used for the active layer. Furthermore, it is limited to semiconductor materials for which bulk wafers of appropriate diameter exist, which is however a problem for many interesting materials like silicon carbide (SiC), gallium arsenide (GaAs) or gallium nitride (GaN).
The second method (SIMOX) is limited to materials for which bulk wafers of appropriate diameters exist and for which ion implantation and formation of a buried oxide layer by post implantation annealing steps is feasible. It is cost intensive due to the required equipment, especially for the ion implantation, and due to long processing times.
Subsequent deposition of heteroepitaxial buried oxide and semiconductor layers on a silicon wafer provide a third method of manufacturing SOI wafers, as for example described for epi-Si/hexagonal Pr2O3/Si systems in the papers H. J. Osten et al., “Growth of crystalline praseodymium oxide on silicon”, Journal of Crystal Growth 235 (2002), 229-234 and T. Schröder et al., “Structure, twinning behavior, and interface composition of epitaxial Si(111) films on hex-Pr2O3(0001)/Si(111) support systems”, Journal of Applied Physics 98 (2005), 123513-1-123513-6. This method includes epitaxially depositing an insulator layer consisting of praseodymium oxide having a hexagonal crystal structure on a silicon substrate wafer and subsequently a silicon layer on the insulator layer.
WO03/096385A2 discloses a method similar to Osten, op. cit., disclosing cesium oxide (CeO2), aluminium nitride (AlN) and lanthanum aluminium oxide (LaAlO3) as materials for the insulator layer. These materials have lattice constants and cubic crystal structures close to those of silicon. Ternary materials like LaAlO3 can be used to adapt the lattice constant of the insulator layer to the overlying semiconductor layer (e.g. silicon-germanium, SiGe). Optionally, a thin layer of amorphous silicon oxide can be grown at the interface between the silicon substrate wafer and the epitaxially deposited insulator layer by a thermal treatment under an oxidizing atmosphere. This layer is preferably formed if a dielectric having a low dielectric constant is required. WO03/096385A2 does not recite any further effects of this silicon oxide layer.
It has been found, however, that SOI wafers produced according to the processes disclosed in WO03/096385A2 have several disadvantages when they are used as substrates for the production of electronic devices, described below.
First, the adaptation of the lattice constant is only possible in a very limited range: La2O3, LaAlO3 and Al2O3 have different crystal structures. La2O3 has a cubic Ia-3 crystal structure whereas Al2O3 has a corundum structure with R3CH symmetry. When both oxides are mixed, a variety of structures results depending on the La/Al ratio, e.g., LaAlO3 has a perovskite-like structure with R-3mR symmetry at room temperature. Due to the different structures it is not possible to mix La2O3 and Al2O3 in any desired ratio from 0 up to 1, i.e. miscibility gaps exist. The perovskite-like structure only exists for La/Al ratios from about 0.8 to about 1.2. In addition, this structure is not suitable for epitaxially depositing monocrystalline cubic semiconductor materials thereon.
Second, incomplete decoupling of the buried oxide lattice from the silicon substrate results in defect generation a) by misfit strain and b) by thermal mismatch due to different thermal expansion coefficients of the materials in the hetero-structure. For example, the latter effect results in microcrack formation in the SOI structures during thermal ramping (annealing as well as cooling down cycles) in the production of the SOI wafer as well as during processing of IC devices.
Third, the insulator layer and the thin additional silicon oxide layer together provide insufficient isolation. Epitaxial oxides exhibit in general rather high leakage currents due to the absence of grain boundaries which are perpendicularly oriented with respect to the current path and which thus block leakage current. Thin amorphous SiO2 layers are also not efficient due to having thicknesses in the regime of direct tunneling phenomena. Thicker SiO2 layers cannot be achieved in every case, and then only if the wafer is annealed at a high temperature. High temperature annealing, however, degrades the crystallinity of the epitaxial oxide layer and thus destroys the basis for perfect growth of the superficial semiconductor layer. This becomes evident because a “repair anneal” is recommended following the oxidation step (WO03/096385A2, page 5 line 16). Furthermore, precise control of the interface state densities is required to avoid hysteretic floating body effects in the buried oxide by parasitic charge trapping effects.